1. Field of the Invention
The invention relates in general to a fabricating method of forming a semiconductor device, and more particularly to a method which employs doping with different kind of dopant of different concentration to change electric field of a semiconductor device.
2. Description of the Related Art
As devices are designed and developed towards a smaller and smaller dimension, a channel length becomes shorter and shorter. The reduced channel length causes a faster operation speed of a device and other short channel effects. According to the formula "E=V/D", in which E is the electric field, V is the voltage, and D is the channel length, providing a constant voltage, the electric field is increased abruptly with reducing the channel length. The abrupt increase of electric field accelerates the electron in the channel. As a consequence, the electric breakdown occurs.
Most of conventional high voltage devices thicken an isolating layer between the gate and the source/drain regions as a means of lowering the horizontal electric field within the channel. Alternatively, the drift regions below the isolation layer and the graded regions beneath the source/drain regions are lightly doped to provide the necessary voltage gradient. The two above measures are capable of increasing junction breakdown voltage in the source/drain regions so that the high voltage devices are able to operate normally despite the application of a high voltage.
In general, the concentration of dopant in the substrate of a high voltage device is constant. The concentration of dopant in the drift region must be increased for enhancing current driving performance, but that may decrease the breakdown voltage of the high voltage device. The high voltage device has a lower breakdown voltage because there is a potential crowding effect forming near the margin of a drain region, so that the breakdown voltage is easily to occur.
In FIG. 1, a cross-section view of a conventional high voltage device structure is illustrated. A field oxide layer 102 and a gate 104 are formed on a P-type semiconductor substrate 100. An N.sup.+ doped region 106 used as a source region and an N.sup.+ doped region 108 used as a drain region are formed in the substrate 100. There is a P-type doped region 110 formed in the substrate 100 under the source region 106. An N.sup.- doped region 112 is set beside the drain region 108 and under the gate 104 and the field oxide layer 102. The formation of the field oxide layer 102 between the gate 104 and the drain region 108, the P-type doped region 110 and the N.sup.- doped region 112 can improve short channel effect.
Since the N.sup.- doped region 112 is set beside the drain region 108, there is still a junction between the drain region 108 and the substrate 100. The potential crowding effect may occur at the source/drain region-substrate junction so that the structure shown in FIG. 1 has a low efficiency of decreasing surface electric field. Furthermore, the structure can not significantly enhance current driving performance.